1. Field of the Invention
The present invention relates to a method of crystallizing amorphous silicon, and more particularly, to a method of fabricating a polycrystalline silicon thin film transistor (TFT). Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving electrical characteristics of the thin film transistor.
2. Discussion of the Related Art
In a conventional process for forming a polycrystalline silicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a Plasma Chemical Vapor Deposition (PCVD) method or a Low Pressure Chemical Vapor Deposition (LPCVD) method. After the amorphous silicon layer has a thickness of about 500 Å (angstroms), it is re-crystallized into a polycrystalline silicon layer by using a crystallization method. The crystallization method is generally classified into one of an Excimer Laser Crystallization (ELC) method, a Solid Phase Crystallization (SPC) method, a Metal Induced Crystallization (MIC) method, and a Metal Induced Lateral Crystallization (MILC).
In the ELC method, an insulating substrate having an amorphous silicon layer formed thereon is heated to a temperature of about 250° C. An excimer laser beam is then applied to the amorphous silicon layer to form a polycrystalline silicon layer. In the SPC method, the amorphous silicon layer is heat-treated at a high temperature for a long time to be crystallized into a polycrystalline silicon layer. In the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal is used for crystallization. In the MIC method, a large-sized glass substrate can be used as an insulating substrate. In the MILC method, a metal is first formed on the amorphous silicon layer, and then the amorphous silicon layer is crystallized. Also in the MILC method, an oxide pattern is formed on a predetermined active portion of the amorphous silicon layer. The amorphous silicon layer becomes polycrystalline silicon by a lateral growth of grains.
The Excimer Laser Crystallization (ELC) method has also been used with some advantages in annealing amorphous silicon. The excimer laser allows areas of an amorphous silicon film to be exposed to very high temperatures for very short periods of time. Theoretically, this offers a possibility of annealing the amorphous silicon at an optimum temperature (less than 400 degrees Celsius) without degrading the underlying substrate upon which the silicon amorphous film is mounted. However, use of this method has been limited by the lack of control over some of the process steps. Typically, an aperture size of the laser is relatively small. Due to the aperture size, power of the laser, and thickness of the amorphous silicon film, multiple laser passes or shots may be required to complete an annealing process. Since it is difficult to precisely control the laser, the multiple shots introduce non-uniformities into the annealing process. Further, the substrates must be annealed serially rather than simultaneously in a furnace. As a result, TFTs made by the ELC method are significantly more expensive.
In the SPC method, a buffer layer is formed on a quartz substrate that can stand a temperature higher than 600° C. The buffer layer serves to prevent a contamination from the quartz substrate. Thereafter, an amorphous silicon layer is deposited on the buffer layer and is sufficiently heat-treated in a furnace at a high temperature so as to form a polycrystalline silicon layer. However, because the SPC method is performed at the high temperature for a long period of time, it is difficult to acquire a desired crystalline silicon phase.
In the process of SPC method, because the crystalline grains develop without a continuous directionality, the polycrystalline silicon layer may have an irregular surface. In a thin film transistor, a gate insulating layer covers the polycrystalline silicon layer. Therefore, if the polycrystalline silicon layer has an irregular surface, the gate insulating layer is also irregularly formed, thereby decreasing a breakdown voltage of the thin film transistor. In addition, the size of the polycrystalline silicon grains formed by the SPC method are very irregular, thereby deteriorating electrical characteristics of a device using the polycrystalline silicon layer. Furthermore, the quartz substrate used for the SPC method is very expensive, thereby increasing the fabrication costs.
Unlike the SPC method that uses an expensive quartz substrate, the MIC method and the MILC method may utilize a relatively inexpensive glass substrate for forming polycrystalline silicon. In the MIC method and the MILC method, however, metal impurities may remain in the polycrystalline silicon network, thereby deteriorating the quality of the polycrystalline silicon layer. To alleviate this residual impurity problem, the conventional art employs the following method, which will be described with reference to FIGS. 1A to 1C and 2A to 2E.
FIGS. 1A to 1C are perspective views illustrating process steps of forming a polycrystalline silicon layer according to the conventional art.
Referring to FIG. 1A, a buffer layer 12 and an amorphous silicon (a-Si:H) layer 4 are sequentially deposited on a substrate 10. The buffer layer 12 is silicon nitride (SiNX) or silicon oxide (SiO2), and prevents alkali substances included in the substrate 10 from spreading into the amorphous silicon layer 4. Thereafter, the amorphous silicon layer 4 is dehydrogenated by a heat-treatment.
Referring to FIG. 1B, a catalytic metal 16 is formed on the surface of the amorphous silicon layer 4. For the catalytic metal 16, Nickel (Ni), Lead (Pb) or Cobalt (Co) is preferably employed. An ion shower method, an ion doping method, a sputtering method or a chemical vapor deposition (CVD) method is employed for the formation of the catalytic metal 16. After forming the catalytic metal, the amorphous silicon layer 4 is heated and then converted into a polycrystalline silicon layer 15 as shown in FIG. 1C.
FIGS. 2A to 2E are cross-sectional views illustrating process steps of forming a thin film transistor having a polycrystalline silicon layer according to the conventional art.
Referring to FIG. 2A, a buffer layer 2 is first formed on the substrate 10. Thereafter, a polycrystalline silicon layer is formed on the buffer layer 2 using the process mentioned with reference to FIGS. 1A to 1C, and then patterned to form an island-shaped active layer 8.
Referring to FIG. 2B, a gate insulation layer 11 is formed on the buffer layer 2 to cover the active layer 8. The gate insulation layer 11 is made of silicon nitride (SiNX), silicon oxide (SiO2), or Tetra Ethoxy Silane (TEOS), for example. Thereafter, a gate electrode 12 is formed on the gate insulation layer 11 and over the active layer 8. The active layer 8 is divided into two areas: a first active area 14 that is an intrinsic silicon area, and second active areas 16 and 17 wherein impurity ions are to be doped. The second active areas 16 and 17 are positioned on respective sides of the first active area 14. After forming the gate electrode 12 over the active layer 8, n-type ions (e.g. phosphorus ions) are doped onto the second active areas 16 and 17. Since the gate electrode 12 is disposed above the first active area 14 and acts as an ion stopper, the dopant, such as n-type ions, is not doped into the first active area 14.
This ion doping is performed to remove residual metal remaining in the island-shaped active layer 8, especially in the first active area 14. During the activation process after ion-doping, the residual catalytic metal left in the first active area 14 beneath the gate electrode 12 diffuses out from the first active area 14 towards the second active areas 16 and 17, and then reacts with the doped ions. In addition, a product resulting from the reaction of the catalytic metal and the doped ions flows out to and accumulates in the interfaces between the gate insulation layer 11 and the second active areas 16 and 17. Therefore, when the gate insulation layer 11 is etched out except a portion between the first active area 14 and the gate electrode 12 after the annealing process, the residual catalytic metal can be removed.
FIG. 2C shows a step of performing an ion-doping process after etching the gate insulation layer 11. As shown in FIG. 2C, a dopant, such as p-type ions, is doped into the second active areas 16 and 17 to form source and drain regions. In this ion-doping process, the gate electrode 12 also serves as an ion-stopper that prevents the p-type ion dopant from penetrating into the first active area 14. The first active area 14 is an intrinsic silicon region, whereas the second active areas 16 and 17 are doped silicon regions. The first active area 14 is centered between the second active areas 16 and 17. The gate insulation layer 11 and the gate electrode 12 are sequentially disposed on the first active area 14.
The above-mentioned dopant includes a group III element, such as boron (B). For example, B2H6 is used as the dopant. After the ion doping is finished, the doped portions 16 and 17 of the island-shaped active layer 8 become a p-type semiconductor.
Referring to FIG. 2D, an interlayer insulator 18 is formed to cover the gate electrode 12, the first active area 14, and the second active areas 16 and 17. A source contact hole 16a and a drain contact hole 17a are formed through the interlayer insulator 18, thereby exposing the second active areas 16 and 17, respectively. The second active areas 16 and 17 are source and drain regions on which source and drain electrodes are formed, respectively.
Referring to FIG. 2E, a source electrode 20 and a drain electrode 22 are formed on the interlayer insulator 18. The source and drain electrodes 20 and 22 electrically contact the source and drain regions 16 and 17, respectively, through the respective source and drain contact holes 16a and 17a. This completes a thin film transistor T having p type polycrystalline silicon source and drain regions.
Thereafter, a passivation layer 26 is formed to cover the source and drain electrodes 20 and 22, and then patterned to form a pixel contact hole 27 that exposes a potion of the drain electrode 22. On the surface of the passivation layer 26, a transparent conductive material is deposited and then patterned to form a pixel electrode 28. Thus, the pixel electrode 28 formed on the passivation layer 26 electrically contacts the drain electrode 22 through the pixel contact hole 27.
In the conventional process of fabricating the polycrystalline silicon TFT, n-type ions are doped onto the polycrystalline silicon layer and then the annealing process is performed to remove the residual catalytic metal. However, although the gate insulation layer formed on the polycrystalline silicon layer is etched out to remove the residual catalytic metal after the annealing process, n-type ions may remain in the second active areas of the polycrystalline silicon layer which the source and drain electrodes contact. Therefore, when p-type ions are doped into the second active areas in a later step, quite complicated process parameters need to be adjusted considering the residual n-type ions, thereby introducing complexities in the process. In addition, the polycrystalline silicon TFT may be deteriorated, if the doping condition is not adequately controlled and adjusted to meet the optimal overall performance when p-type ions are doped.